Vertical antifuse memory cells conventionally comprise a decoupling element, such as a PN junction diode, and an antifuse element electrically connected in series with the blocking element. The memory cell is connected between a bit line and word line. Initially, the antifuse exists in a nonconductive state. To program the memory cell, a voltage is selectively impressed across it to short the antifuse and thereafter cause the antifuse to exist in a highly conductive state. Shorted antifuse memory cells return a logical "1" on the bit line, and unshorted antifuse memory cells return a "0" on the bit line inherently.
Prior art antifuse constructions are shown in the following publications: "Memories," Electronics, Vol. 53, No. 23, p. 141 (Oct. 23, 1980); and "A 16K PROM USES VERTICAL FUSE," Electronics, Vol. 55, No. 4, p. 184 (Feb. 24, 1982). One of these references discloses a vertical antifuse where the memory cell comprises a polysilicon emitter above a bipolar transistor decoupling element. A layer of aluminum is disposed above the polysilicon emitter. In order to program the cell, a voltage is impressed across the aluminum and the base of the decoupling element in order to raise the temperature of the aluminum and the poly emitter up to their eutectic point, causing aluminum to spike through the emitter-base junction. This short-out of the emitter based junction leaves the base/collector junction as the decoupling element of the programmed memory cell. A disadvantage of this technique is that the current has to be sufficiently high (on the order of 100 milliamperes) to diffuse through 1500-2500 Angstroms of single crystal silicon, in addition to the polysilicon emitter. A problem exists in attempting to control the diffusion of the aluminum so that it does not short out the base/collector junction as well. The base must be wide enough to avoid the spike-through of aluminum to the collector, shorting out the entire decoupling element. This poses a restriction on scaling.
Another antifuse approach is disclosed by M. Tanimoto, et al., "A Novel Programmable 4K-Bit MOS PROM Using A Polysilicon Resistor Applicable To On-Chip Programmable Devices," IEEE J. Solid State Circuits, Vol. SC-17, No. 1, pp 62-68 (February 1982). An initially nonconductive polysilicon resistor fuse element is disclosed in this reference and is used in MOS applications. The resistor fuse is surrounded by phosphorus oxide. Autodoping of the polysilicon fuse by the phosphorus will occur during subsequent high temperature fabricating steps to drop the resistance of the fuse element to below 100 Kilohms. Thereafter, the resistance is further reduced by the diffusion of arsenic in order to program the antifuse element. Because arsenic and phosphorus are not highly conductive dopants, Tanimoto's resistor fuse provides an electrical path of relatively high resistance between the word line and the bit line as opposed to a path created by a highly conductive metal diffusant such as aluminum.
In view of the above problems, a need has arisen in the industry to provide a vertical antifuse structure that avoids the danger of destruction of a bipolar decoupling element upon programming and that simultaneously provides a low-resistance conductive path upon programming the cell.